1. Field of the Invention
The present invention relates to a fuse target and, more particularly, to a fuse target and a method of forming the fuse target in a copper process flow.
2. Description of the Related Art
A fuse is a device that provides a low-resistance current path between two conductive lines when the fuse is unprogrammed, and a high-resistance current path between the two conductive lines when the fuse is programmed. Fuses are commonly used to trim semiconductor devices, such as resistors, to form precision analog devices.
A fuse target is a device that has a unique signature which can be detected by an optical recognition system. For example, an optical recognition system can detect the shape and reflectivity of a fuse target, and then determine the position of the fuse target. The fuse target has a known positional relationship with respect to the semiconductor fuse. As a result, the position of the semiconductor fuse can be determined from the position of the fuse target.
FIGS. 1A-1C show views that illustrate a prior-art semiconductor wafer 110 with a fuse and a fuse target. FIG. 1A shows a plan view, while FIGS. 1B and 1C show cross-sectional views taken along line 1B-1B of FIG. 1A. As shown in FIGS. 1A-1C, semiconductor wafer 110 includes a semiconductor substrate 112 and a metal interconnect structure 114 that is connected to semiconductor substrate 112.
Semiconductor substrate 112 includes a number of structures that are formed in and on substrate 112. The structures, which include resistors, transistors, capacitors, diodes, and similar devices, have a number of conductive contact regions 112C, such as the ends of a resistor and the terminals of a transistor. In the present example, the resistors include a trim resistor that has a first polysilicon resistive segment RS1 with a conductive contact region 112C at an end RE1, and a second polysilicon resistive segment RS2 with a conductive contact region 112C at an end RE2.
Metal interconnect structure 114, in turn, is a multi-layered structure that electrically interconnects together the various devices that are formed on substrate 112 to realize an electrical circuit. Metal interconnect structure 114 includes a number of contacts 114C that touch the conductive contact regions 112C (either directly or via silicide).
Metal interconnect structure 114 also includes a number of metal-1 traces 114-M1 that are connected to the contacts 114C, a number of metal-2 traces 114-M2, a number of metal-3 traces 114-M3, and a number of metal-4 traces 114-M4. In the present example, the metal-1 traces 114-M1, the metal-2 traces 114-M2, the metal-3 traces 114-M3, and the metal-4 traces 114-M4 are implemented with aluminum. Further, selected regions on the top surfaces of the metal-4 traces 114-M4 are exposed to the external world, and function as bond pads 114P that provide an external electrical connection point.
In addition, metal interconnect structure 114 includes a number of inter-metal vias 114V that connect the metal-1 traces 114-M1 and the metal-2 114-M2 traces together, the metal-2 traces 114-M2 and the metal-3 114-M3 traces together, and the metal-3 traces 114-M3 and the metal-4 114-M4 traces together.
Metal interconnect structure 114 further includes a planarized insulation region 1141 that touches semiconductor substrate 112, the conductive contacts 114C, the metal-1 traces 114-M1, the metal-2 traces 114-M2, the metal-3 traces 114-M3, the metal-4 traces 114-M4, and the inter-metal vias 114V. In the present example, insulation region 1141 includes a region of oxide 114L and an overlying passivation layer 114U. Passivation layer 114U, which has a top surface 114S, can be implemented with, for example, oxide, nitride, or a combination of oxide and nitride.
Metal interconnect structure 114 further includes a fuse 116 which has a first end FE1 and a second end FE2. First end FE1 makes an electrical connection with the structure to be trimmed which, in the present example, is end RE1 of polysilicon resistive segment RS1 of the trim resistor. Similarly, second end FE2 makes an electrical connection with the structure to be trimmed which, in the present example, is end RE2 of polysilicon resistive segment RS2 of the trim resistor. Fuse 116 is illustrated in the present example as a short thin metal-2 trace, although fuse 116 can be implemented in other metal layers.
In addition, metal interconnect structure 114 includes a stacked metal ring structure MR1 that is formed around fuse 116 to protect adjacent regions of wafer 110 from fuse 116 during programming. Metal ring structure MR1 includes a metal-1 trace 114-M1 that is formed around fuse 116 as a metal-1 ring M1R1, and a metal-2 trace 114-M2 that is formed around fuse 116 as a metal-2 ring M2R1. Further, metal ring structure MR1 includes a metal-3 trace 114-M3 that is formed around fuse 116 as a metal-3 ring M3R1, and a metal-4 trace 114-M4 that is formed around fuse 116 as a metal-4 ring M4R1.
The metal rings M1R1, M2R1, M3R1, and M4R1 are electrically connected together by way of a number of inter-metal vias 114V, but are electrically isolated from all other conducting structures. (Only one fuse 116 is shown for clarity. A large number of fuses 116 can lie within stacked metal ring MR1 (a bank of fuses), and wafer 110 can include a large number of fuse banks.) Metal interconnect structure 114 also includes a fuse opening 118 in planarized insulation region 1141 that exposes a thin layer 114T of planarized insulation region 1141 that lies on fuse 116.
In addition, metal interconnect structure 114 includes a fuse target 120 that has a known positional relationship with fuse 116. (Only one fuse target 120 is shown for clarity. Fuse targets are commonly located in the corners of a region that surround the fuse banks.) In the present example, fuse target 120 is illustrated as an exposed, electrically-isolated, L-shaped metal-4 trace 120M that sits on a pedestal 122 surrounded by a trench 124.
Metal interconnect structure 114 further includes a stacked metal ring structure MR2 that is formed around fuse target 120 to protect adjacent regions of wafer 110 from fuse target 120 during the formation of fuse opening 118 and trench 124. Metal ring structure MR2 includes a metal-1 trace 114-M1 that is formed around fuse target 120 as a metal-1 ring M1R2, and a metal-2 trace 114-M2 that is formed around fuse target 120 as a metal-2 ring M2R2.
Metal ring structure MR2 also includes a metal-3 trace 114-M3 that is formed around fuse target 120 as a metal-3 ring M3R2, and a metal-4 trace 114-M4 that is formed around fuse target 120 as a metal-4 ring M4R2. The metal rings M1R2, M2R2, M3R2, and M4R2 are electrically connected together by way of a number of inter-metal vias 114V, but are electrically isolated from all other conducting structures.
In operation, in the native or unprogrammed state, which is shown in FIG. 1B, fuse 116 provides a low-resistance current path between the resistive segments RS1 and RS2. To program fuse 116, an optical recognition system is used to detect the shape and reflectivity of fuse target 120, and then determine the position of fuse target 120. Once fuse target 120 has been located, the position of fuse 116 is determined from the known positional relationship.
After the position of fuse 116 has been determined, a laser beam with a predefined output power is directed to that position. Fuse 116 is heated by the laser until a portion thin insulation region 114T and a portion of fuse 116 evaporate away to leave two physically separated sections of fuse 116. The two physically separated sections of fuse 116, in turn, provide an open current path between the polysilicon resistive segment RS1 and RS2. FIG. 1C shows semiconductor wafer 110 after fuse 116 has been programmed.
One problem with fuse target 120 is that fuse target 120 is not compatible with the current-generation processes that are used to form copper-topped interconnect structures. To reduce the resistance of a metal interconnect structure, current-generation processes commonly form the top one or more layers of metal traces from copper.
FIGS. 2A-2F show a series of cross-sectional views that illustrate a prior-art method 200 of forming copper traces that lie over a top layer of aluminum traces. As shown in FIG. 2A, method 200 is practiced on a conventionally-formed semiconductor wafer 210 that includes an interconnect structure which has a top layer of aluminum traces 212.
As further shown in FIG. 2A, the method begins by depositing a layer of passivation (non-conductive) material 214, such as a layer of nitride, oxide, or a combination of oxide and nitride, over the top surfaces of the aluminum traces 212. The method continues by forming and patterning a mask 216 on passivation layer 214. Following this, the exposed regions of passivation layer 214 are etched to form openings 220 that expose the top surfaces of the aluminum traces 212 of the interconnect structure. Mask 216 is then removed.
As shown in FIG. 2B, after mask 216 has been removed, a seed layer 222 is formed on passivation layer 214 and the exposed regions of the aluminum traces 212. Seed layer 222 typically includes a layer of titanium (e.g., 300 Å thick) and an overlying layer of copper (e.g., 3000 Å thick). The titanium layer enhances the adhesion between the underlying aluminum traces 212 and the overlying layer of copper. Next, a mask 224 is formed and patterned on seed layer 222 to have a number of openings 226 that expose the number of openings 220.
As shown in FIG. 2C, following the formation and patterning of mask 224, copper is electroplated to form a number of copper traces 230 that touch the top surfaces of the aluminum traces 212. Each of the copper traces 230 has a top surface 230T. After the copper traces 230 have been formed, mask 224 is removed, followed by the removal of the underlying regions of seed layer 222.
As shown in FIG. 2D, the removal of seed layer 222 from the top surface of passivation layer 214 forms a number of spaced-apart seed portions 222P. The seed portions 222P touch the aluminum metal-4 trace 114-M4, passivation layer 214, and the copper traces 230. After mask 224 and the underlying regions of seed layer 222 have been removed, an adhesion enhancing layer 232, such as titanium, is deposited on the exposed regions of passivation layer 214 and the copper traces 230. Following this, a metallic layer 234, such as aluminum, aluminum-copper, or gold, is deposited on adhesion enhancing layer 232. Once metallic layer 234 has been formed, a mask 236 is formed and patterned on metallic layer 234.
As shown in FIG. 2E, after mask 236 has been formed and patterned, the exposed regions of metallic layer 234 are etched away to form a number of spaced-apart metal bond pads 240 that lie over selected regions of the top surfaces 230T of the copper traces 230 to form external electrical connection points.
In addition to removing the exposed regions of metallic layer 234, as further shown in FIG. 2E, the underlying regions of adhesion enhancing layer 232 are also etched away to form a number of spaced-apart adhesion enhancing pads 242 that lie between and touch the copper traces 230 and the metal bond pads 240.
Once the etch has been completed, as shown in FIG. 2F, mask 236 is removed to complete method 200. Alternately, after mask 236 has been removed, solder balls or solder bumps can be attached to the metal bond pads 240, or thin bonding wires can be bonded to the metal bond pads 240.
The problem with method 200 is that when method 200 is applied to a semiconductor wafer that includes an aluminum fuse and an aluminum fuse target, the chemistry used to remove the un-used regions of seed layer 222 also attacks the exposed aluminum of the fuse target. As a result, following the formation of a layer of copper traces, the exposed aluminum of the fuse target, such as fuse target 120, can be damaged to the point of where the optical recognition system can no longer detect the fuse target. When this occurs, the position of the fuse can no longer be identified, and the fuse can no longer be programmed.
As a result, there is a need for a fuse target that is compatible with the current-generation fabrication processes that are used to form copper-topped interconnect structures.